1. Field of the Invention
The present invention relates to a semiconductor device such as a mass storage mask ROM.
2. Background of the Invention
As shown in FIG. 10, a semiconductor device is generally provided with a plurality of external connection pins 1 to 32 projecting from both side edges of a package 21 having a rectangular plane shape. In such a conventional semiconductor device, further, a power supply pin Vcc (32) and a GND terminal Vss (16) are arranged on positions which are most separate from each other on a diagonal line of the package 21, as shown in FIG. 10. In other words, the power supply pin Vcc (32) and the GND terminal Vss (16) are arranged on right upper and left lower portions of the package 21 shown in FIG. 10 respectively. Address input terminals A.sub.11 (25) to A.sub.18 (31) are arranged on positions relatively close to the power supply pin Vcc (32), while address input terminals A.sub.0 (12) to A.sub.16 (2) are arranged on side edge portions which are opposed to the address input terminals A.sub.11 (25) to A.sub.18 (31). Further, data output terminals D.sub.0 (13) to D.sub.2 (15) are arranged on positions relatively close to the GND terminal Vss (16), while data output terminals D.sub.3 (17) to D.sub.7 (21) are arranged on side edge portions which are opposed to the data output terminals D.sub.0 (13) to D.sub.2 (15) and the GND terminal Vss (16). Referring to FIG. 10, numeral 1 denotes a spare pin (NC), numerals 22 and 24 denote control terminals (/CE and /OE) such as chip enable terminals, and numeral 23 denotes an additional input terminal A.sub.10. Referring to FIGS. 11 and 12, numeral 35 denotes a chip, numeral 35a denotes an internal circuit provided in the chip 35, and numeral 35b denotes a die pad for die-bonding the chip 35.
When a memory having a large data width of 8 bits or 16 bits is designed, a pad Vcc wire 31 is separated from a Vcc wire 33 for the internal circuit 35a while a pad Vss wire 32 is separated from a Vss wire 34 for the internal circuit 35a in general, in order to reduce an influence exerted by a data output noise on the chip 35. In pin arrangement of such a conventional semiconductor device, the chip 35 shown in FIG. 11 is formed in the package 21. Namely, it is necessary to wire the Vcc wire 31 and the Vss wire 32 for pads 36 and 37 provided on upper and lower portions of the chip 35 respectively, and the chip size is increased due to the wires 31 and 32 passing through left and right sides of the chip 35. While it is preferable to wire different Vcc/Vss wires for address input pads 41 and data output pads 42 in order to reduce influences exerted by output noises on input wires, the chip size is further increased if the address input pads 41 and the data output pads 42 which are arranged on the lower portion of the chip 35 are separated from each other and it is difficult to provide such a product in practice. When the chip 35 is sealed in the package 21 as shown in FIG. 12, further, a pin 45 corresponding to the central portion of the chip 35 must be arranged adjacently to a side portion of the chip 35. Thus, it is necessary to prevent bonding wires 47 and 47a for connecting the pin 45 and another pin 45a with pads 46 and 46a of the chip 35 respectively from shorting. In general, therefore, the pad 46 which is arranged adjacently to the pad 46a is displaced from the remaining pads, as shown in FIG. 12. In this case, however, only the two pads 46 and 46a provided on a corner of the chip 35 are arranged in two columns, although most of the pads are aligned with each other. In other words, an additional area is required for the corner of the chip 35, as compared with the remaining portion. When the internal circuit 35a is formed by a memory cell array, the array is incomplete if a memory cell is omitted from a part of the corner portion. Therefore, it is necessary to reduce the column or row number of X-directional or Y-directional memory cells provided in the memory cell array by several on each end. Thus, the number of the memory cells is remarkably reduced contrarily to requirement for high density.